The present invention relates generally to non-volatile memory circuits, and more particularly relates to a non-volatile memory circuit comprising a plurality of memory cells including a ferroelectric gate field-effect transistor (FeGFET) and techniques for fabricating a FeGFET device.
Using ferroelectric material in the manufacture of non-volatile memories has been well-established. For instance, U.S. Pat. No. 3,832,700 issued to Wu et al. describes a ferroelectric memory device which utilizes remnant polarization of a ferroelectric film as the storage mechanism. This structure may be considered analogous to a conventional electrically erasable programmable read-only memory (EEPROM). U.S. Pat. No. 4,873,664 issued to Eaton, Jr. describes a semiconductor memory device utilizing memory cells having a ferroelectric capacitor coupled to a bit line via a transistor, much like a conventional dynamic random access memory (DRAM).
Both DRAM-like memory cell structures and EEPROM-like cell structures have been proposed for use in ferroelectric memory products. Modern ferroelectric memory products exploit the DRAM-type cell structure exclusively. Such structures have both the advantage of minimizing integration complexity, by separating the storage capacitor from the silicon devices region, and improving cell density, by stacking the ferroelectric apacitor on top of the silicon devices.
Although this type of memory may be easy to fabricate, the DRAM-like cell structure has several disadvantages, including coupled noise sensitivity, coupled noise generation, large power consumption and low overall performance. The density of the memory device suffers compared to conventional DRAM due, at least in part, to the use of a ferroelectric capacitor plate electrode and the need for a special driver circuit. Moreover, because the driver circuit must be capable of driving a heavily loaded wire during read and write operations, it is particularly slow. Additionally, a boosted high voltage signal is required for both read and write operations. This results in significant noise coupling between signal lines as well as high power consumption. Although there has been some recent progress in terms of density, power consumption and material-related problems, several fundamental issues remain in ferroelectric memories exploiting a DRAM-type cell structure which prevent this type of conventional memory from being used in high density, high speed and/or low power applications.
As previously stated, EEPROM-like memory cell structures have been suggested for use in fabricating non-volatile memory devices since about 1974. However, fabricating ferroelectric gate dielectric on silicon introduces several material-related problems as well as electrical problems, including, for example, dipole instability, since silicon channels generally fail to provide enough carrier density to neutralize the depolarization fields that impair ferroelectric retention (see, e.g., P. Wurfel and I. B. Batra, Phys Rev B Vol. 8, 5126 (1973)). Additionally, the write operation to reverse the polarization orientation in a memory cell is difficult to accomplish using conventional ferroelectric memory structures.
There exists a need, therefore, for an improved ferroelectric structure that can be used to fabricate non-volatile memory devices which does not exhibit the above-noted disadvantages present in conventional ferroelectric memory devices.
The present invention provides techniques for forming a ferroelectric gate field-effect transistor device and a non-volatile memory architecture employing such devices.
In accordance with one aspect of the invention, a semiconductor device comprises a field-effect transistor (FET) formed on a silicon substrate, the FET including a drain region and a source region, and a ferroelectric gate field-effect transistor (FeGFET) for storing a logical state of the semiconductor device. The FeGFET comprises a gate electrode formed on an upper surface of the substrate and in electrical contact with one of the drain region and the source region of the FET, a ferroelectric gate dielectric layer formed on an upper surface of the gate electrode, an electrically conductive channel layer formed on an upper surface of the ferroelectric gate dielectric layer, and first and second drain/source electrodes, the first and second drain/source electrodes being formed on and electrically contacting the channel layer at laterally opposing ends of the channel layer. The ferroelectric gate dielectric layer is selectively polarizable in response to a potential applied between the gate electrode and at least one of the first and second drain/source electrodes.
In accordance with another aspect of the invention, a vertical FeGFET device comprises a substrate and a first drain/source electrode formed on an upper surface of the substrate. An electrically conductive channel region is formed on an upper surface of the first drain/source electrode and electrically contacting the first drain/source electrode. The FeGFET device further comprises a ferroelectric gate region formed on at least one side wall of the channel region, at least one gate electrode electrically contacting the ferroelectric gate region, and a second drain/source electrode formed on an upper surface of the channel region and electrically contacting the channel region. The ferroelectric gate region is selectively polarizable in response to a potential applied between the gate electrode and at least one of the first and second drain/source electrodes.
A non-volatile memory cell formed in accordance with one embodiment of the present invention comprises a first FET, at least a second FET, and a FeGFET for storing a logical state of the memory cell. The FeGFET is operatively coupled to the first and second FETs. Each of the first and second FETs include a control input for selectively accessing the FeGFET in response to a control signal presented thereto.
A non-volatile memory array formed in accordance with another embodiment of the invention comprises a plurality of memory cells, at least one of the memory cells including a FeGFET for storing a logical state of the memory cell, the FeGFET having a first drain/source terminal and a second drain/source terminal. The memory cell further includes a first switch operatively coupled to the first drain/source terminal of the FeGFET and at least a second switch operatively coupled to the second drain/source terminal of the FeGFET. A plurality of bit lines and word lines arc operatively coupled to the memory cells for selectively reading and writing one or more memory cells in the memory array.